PIC18F2XK20/4XK20
DS41297F-page 20
Advance Information
2009 Microchip Technology Inc.
3.3
Data EEPROM Programming
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair EEADRH:EEADR) and a
data latch (EEDATA). Data EEPROM is written by
loading EEADRH:EEADR with the desired memory
location, EEDATA with the data to be written and initiat-
ing a memory write by appropriately configuring the
EECON1 register. A byte write automatically erases the
location and writes the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1).
The write begins on the falling edge of the 24th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, PGC
must be held low for the time specified by parameter
P10 to allow high-voltage discharge of the memory
array.
FIGURE 3-6:
PROGRAM DATA FLOW
FIGURE 3-7:
DATA EEPROM WRITE TIMING DIAGRAM
Start
Start Write
Set Data
Done
No
Yes
done?
Enable Write
Sequence
Set Address
WR bit
clear?
No
Yes
n
PGC
PGD
PGD = Input
00
0
BSF EECON1, WR
4-bit Command
12
3
4
1
215 16
P5
P5A
P10
12
n
Poll WR bit, Repeat until Clear
16-bit Data
Payload
12
3
4
1
215 16
12
3
P5
P5A
4
1
2
15 16
P5
P5A
00
0
MOVF EECON1, W, 0
4-bit Command
00
4-bit Command
Shift Out Data
MOVWF TABLAT
PGC
PGD
(see below)
(see Figure 4-4)
PGD = Input
PGD = Output
Poll WR bit
P11A
P5A
2 NOP commands
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